Automated PR - 2026-05-11
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@@ -48,7 +48,7 @@ from ltx_core.model.video_vae import TilingConfig, VideoEncoder
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from ltx_core.quantization import QuantizationPolicy
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from ltx_core.tiling import DimensionTilingConfig, TileCountConfig
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from ltx_core.tools import VideoLatentTools
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from ltx_core.types import VideoLatentShape
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from ltx_core.types import VideoLatentShape, VideoPixelShape
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from ltx_pipelines.utils.blocks import (
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DiffusionStage,
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ImageConditioner,
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@@ -412,7 +412,22 @@ class HDRICLoraPipeline:
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high_quality_hdr=high_quality_hdr,
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)
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)
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with self.stage_2.model_context() as transformer:
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# video_tools is required by TiledDataParallelBuilder when stage_2 is
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# wrapped for multi-GPU
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stage2_video_tools = VideoLatentTools(
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VideoLatentPatchifier(patch_size=1),
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VideoLatentShape.from_pixel_shape(
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VideoPixelShape(
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batch=1,
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frames=gen_num_frames,
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height=gen_h,
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width=gen_w,
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fps=frame_rate,
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)
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),
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frame_rate,
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)
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with self.stage_2.model_context(video_tools=stage2_video_tools) as transformer:
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phase_latent = upscaled_video_latent
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for phase_idx, (tiling, sigmas_list, use_ic) in enumerate(
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zip(stage2_tilings, stage2_sigmas, stage2_use_ic_lora, strict=True)
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@@ -542,10 +557,10 @@ class HDRICLoraPipeline:
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"""
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# Cast to float32 so tiled-decode accumulation buffers and blending
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# masks run in full precision, avoiding bfloat16 seam artifacts.
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# Request float32 [0, 1] output — apply_hdr_decode_postprocess expects it.
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# apply_hdr_decode_postprocess expects float32 [0, 1].
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latent = latent.float()
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decoded = torch.cat(
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list(self.video_decoder(latent, tiling_config, generator, output_dtype=torch.float32)),
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[chunk.float() for chunk in self.video_decoder(latent, tiling_config, generator)],
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dim=0,
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)
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decoded = rearrange(decoded, "f h w c -> 1 c f h w")
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